1. Field of the Invention
The present invention relates, in general, to a semiconductor device and a method for fabricating the same and, more particularly, to an etch barrier structure which prevents the deterioration of element-isolation properties as well as affords a larger allowable alignment error in the etching processes for contact holes, thereby achieving the high integration of semiconductor devices.
2. Description of the Prior Art
Much of the advance in the high integration of semiconductor devices is dependent on the size of memory cells, which is, in turn, greatly determined by the design rule. That is, if the design rule is more strictly applied, the memory cells are made smaller in size, which allows a higher integration of semiconductor devices. Also, the memory capacity increases with the high integration of semiconductor devices. However, the high integration also give an increase to the size of memory chips.
It is, therefore, requisite for the improvement in the productivity and throughput of semiconductor device that the memory chip should be reduced in size by designing memory cells as small in size as possible under the same design rule.
The high integration of semiconductor devices is based on the progress which has been made in many techniques for semiconductor devices. Particularly, brilliant development has been achieved in lithography. Lithography, which plays a pivotal role in the high integration of semiconductor devices, is divided into a formation technique of fine patterns and an alignment technique of functional layers in a semiconductor device structure.
Up to now, the formation technique has been greatly advanced but not equally with the alignment technique. Thus, the limitation of this technique is a limiting factor to the reduction of the size of memory cells.
A self-alignment concept was suggested to overcome this limitation but is difficult to put into practice.
In a memory cell of a semiconductor device, a contact must be formed in an active region of a semiconductor substrate. For example, in each memory cell of DRAM, a contact hole is formed to connect a bit line and an electrode of a capacitor with an active region of a semiconductor substrate.
In this regard, a description will be given of an example in that the size of memory cells is increased owing to the limitation of the alignment technique in a conventional semiconductor device, in connection with some drawings, below.
Referring to FIGS. 1 and 2, there are, respectively, cross-sectionally and longitudinally shown, a memory cell of DRAM.
In order to fabricate the memory cell, first, a field oxide 3 is formed on a semiconductor substrate 1, to separate semiconductor elements, followed by the formation of a transistor structure in an active region, as shown in the figures.
Then, a first interlayer insulating film made of silicon oxide is formed between two word lines 5 over the active region and selectively etched to form a first contact hole 9.
Thereafter, a first conductive layer (not shown) is deposited over the first interlayer insulating film 7 to fill the first contact hole 9 and selectively patterned to form a bit line 11.
Over the resulting structure including the bit line 11 and the first interlayer insulating film 7 is deposited a blanket of a second interlayer insulating film 12 which is, then, selectively opened to form a second contact hole 13.
Subsequently, a second conductive layer (not shown) is constructed over the entire surface of both the second contact hole 13 and the second interlayer insulating film 12 so as to fully fill the second contact hole 13, followed by the patterning of the second conductive layer, to give a storage electrode 15.
Finally, after a dielectric film (not shown) is provided for the storage electrode 15, a plate electrode 17 is formed over the dielectric film, to produce a memory cell of DRAM.
This conventional fabricating technique have a significant problems. There inevitably occurs an alignment error when the lithography process for forming the first contact hole is carried out. If the alignment error is so large that it is directed to the word line, when the interlayer insulating film is etched to form the first contact hole, the field oxide is etched at its edge, too, and thus, the element isolation becomes poor. This is attributed to the fact that the interlayer insulating film and the field oxide are silicon oxides which are identical in etch selection ratio.
On the other hand, if the alignment error widely occurs in a perpendicular direction to the word line, a shortage occurs between the word line and the bit line. This shortage can be overcome by recruiting an insulating film spacer into the side wall of the word line; however, in order to prevent the field oxide from being etched at its edge, the active region must be designed to have a wide width in the direction of the word line, leading to an increase in the size of cell. Thus, such an alignment error is a great impediment in reducing the size of memory cell.
Similarly, there occurs a problem upon the formation of the second contact hole. For example, if a large alignment error occurs in a perpendicular direction to the word line, the field oxide is etched at its edge and thus, the active region must be designed to be sufficiently large.
Consequently, the conventional technique has a great difficulty in highly integrating semiconductor devices.